Design Verification Engineer

Design Verification Engineer
Viseu
Viseu, Viseu District, Portugal

ADVANS Portugal is looking for experienced Design Verification Engineers to our new Lisbon offices.

This is a
- time hybrid role.

Key Responsibilities / Duties:

• Develop and execute verification plans based on design specifications.
• Create testbenches and test cases using System
  Verilog/UVM or equivalent tools.
• Perform simulations and debug design issues in collaboration with design teams.
• Conduct functional, regression, and coverage testing to ensure design correctness.
• Analyze coverage metrics and enhance test cases to meet verification goals.
• Document test procedures, results, and track issues through resolution.

Qualification Requirements:

• BSc or MSc in Computer Science, Electronics, Automation or related software disciplines
• years of experience in digital verification, with expertise in UVM/System
  Verilog or Specman/e.
• Strong background in digital electronics, ASIC/FPGA design.
• Proficiency in system architecture including processor architecture.
• Experience in debugging Gate-Level Simulations (GLS) and timing closure.
• Solid understanding of C/C++ and familiarity with scripting tools (Python, Perl, Tcl).
• Excellent English communication skills.

Benefits:

• Integration program in a professional, young & dynamic team
• Professional development opportunities
• Competitive salaries & benefits
• Health insurance
• International work environment