Physical Design Engineer -#20003

Job Summary

• We are seeking a skilled Physical Design Engineer to join our chip development team. In this role, you will be responsible for implementing and optimizing the physical layout of complex ASICs from RTL to GDSII.
• You’ll collaborate closely with RTL design, verification, and DFT teams to ensure successful
  - out of
  - performance,
  - power silicon designs.

Key Responsibilities

• Own and execute physical design tasks including floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification (LVS/DRC).
• Work on timing closure using STA tools and fix violations across multiple PVT corners.
• Perform IR drop and EM analysis, drive fixes to meet power integrity requirements.
• Collaborate with
  - functional teams including RTL, DFT, packaging, and manufacturing.
• Debug issues across Pn
  R, DRC/LVS, and timing flows, and provide
  - cause analysis and solutions.
• Contribute to flow development and automation to improve quality and efficiency.

Required Qualifications

• B. Sc. / M. Sc. in Electrical Engineering or equivalent.
• 7+ years of experience in ASIC physical design with a proven
  - out record.
• Strong
  - on experience with
  - standard tools (e. g. , Innovus, ICC2, Prime
  Time, Voltus, Calibre).
• Solid understanding of timing, signal integrity, IR drop, and physical verification. Good scripting skills (TCL, Python, or Perl) for flow automation and debug.
• Excellent
  - solving and communication skills.

Preferred Qualifications

• Experience with hierarchical design methodologies.
• Exposure to
  - power design techniques (UPF). Familiarity with advanced nodes (7nm, 5nm or below).