Sr. Physical Digital Design Engineer Lisboa

Sr. Physical Digital Design Engineer
Lisboa
Lisboa, Lisboa, Portugal

Here is a refined version of the job description with improved formatting for clarity and readability:

Sr. Physical Digital Design Engineer, Lisbon

Client: Monolithic Power Systems

Location: Lisbon, Portugal

Job Category: Other

EU work permit required: Yes

Job Reference: c9381ab734dd

Job Views: 3

Posted: 25. 04. 2025

Expiry Date: 09. 06. 2025

Job Description:

Job Summary:

We are seeking a Sr. Physical Digital Design Engineer to join our team of Design Engineers in Europe. This
- site role involves responsibility for physical design and implementation, establishing methodologies, and flow automation.

The engineer will work on digital design implementation and verification of
- signal ICs using standard EDA tools. Projects include designing power management and
- signal functions for markets such as broadband, telecom, automotive, and consumer electronics.

Essential Functions:

• Responsible for physical design, development, & verification of digital/mixed-signal ICs.
• Chip & block floorplanning, power/clock distribution, chip assembly, P&R, STA, LVS/DRC closure.
• Collaborate with digital/analog design teams for physical implementation and custom blocks.
• Develop automated environments for RTL-to-PNR workflows using
  - level languages and devops practices.

Qualifications:

• Advanced degree in Electrical Engineering, Computer Science, or equivalent.
• 3-5 years of Physical Digital Design experience preferred.
• 2+ years ASIC design, verification, or related experience preferred.
• Proficient in English communication and teamwork.
• Ability to work independently, follow specifications, and meet milestones.
• Strong knowledge of ASIC development processes and digital design techniques.
• Experience with programming and scripting languages like Perl, TCL, Unix.
• Expertise in Verilog/System
  Verilog, synthesis, LEC, CTS, DFT, RC extraction, STA, LVS/DRC, and physical verification tools (Cadence or Synopsys preferred).
• Desired experience includes advanced nodes below 16nm, SOC design, hierarchical STA, power management, and FPGA development.